Very low-Power Sampled-Data Σ∆ Architectures for Wireline and Wireless Applications

The sigma delta technique is an attractive approach for many communication applications. The possible alternatives are the use of continuous-time or sampled data modulators. This paper discusses various circuit techniques that enable very low power with switched capacitor architectures. The target applications are WCDMA and ADSL. Circuit implementations show that the use of techniques like use of a single op-amp for high-order architectures, op-amp sharing, time-interleaved and minimization of the op-amp voltage swing obtain figure of merits in the order of fraction of pJ/con.-level.